The present invention relates to a semiconductor memory device having redundant memory cells, particularly to the function of testing the redundant memory cells.
A semiconductor memory device is manufactured by collectively fabricating a plurality of storage circuits in a succession of wafer processes. The fabricated separate storage circuits are to be selected by address signals. Therefore, when the selectable storage circuits have even a single defect, the semiconductor memory device is an unusable defective item. Particularly, as the individual memory devices are reduced in size and increased in the integration degree to grow storage capacity, it is hard to manufacture flawless semiconductor memory devices.
On this account, paying attention that the semiconductor memory device is configured by arranging a plurality of storage circuits having the same patterns, a method is adopted that a substitute storage circuit is prepared beforehand and a storage circuit with a defect is replaced by the substitute storage circuit when the storage circuit originally used has the defect.
However, the traditional DRAM has the following problem. When redundant cells are tested, a probe is brought into contact with individual pads to apply high-level signals. However, it could not be confirmed from outside whether to correctly set the conditions for testing the redundant memory cells inside the device. Therefore, even though the redundant memory cells are not tested appropriately because of logic errors in a test circuit, defects in the circuit patterns formed or contact failure of the probe, such a test result sometimes shows that the redundant memory cell is normal.